/*******************************************************************************

    COPYRIGHT (C) LAB601, Southeast University
    ----------------------------------------
    File Name:      PCI7600.v
    Title:          PCI 7600GT Top Design
    Author:         Len D.
    Email:          neldon@gmail.com
    Revision:       0.8
    Date:           2009-11-09
    Description:    1) Top module.
    Other:          //
    ----------------------------------------
    History
    ----------
    Date        Rev     By          Description
    ----------  ------  ----------  ----------------------------------------
    2009-XX-XX  1.0     Len D.      a)
    
*******************************************************************************/
module PCI7600(
                // pci interface.
                PIN_PCICLK,
                PIN_FRAME_N,
                PIN_IRDY_N,
                PIN_IDSEL,
                PIN_DEVSEL_N,
                PIN_TRDY_N,
                PIN_STOP_N,
                PIN_PCI_AD,
                PIN_CBE_N,
                PIN_REQ_N,
                PIN_GNT_N,
                PIN_PAR,
                PIN_SERR_N,
                PIN_PERR_N,
                PIN_INTA_N,

                // sdram interface.
                PIN_SDRAMCLK,
                PIN_CS_N,
                PIN_CKE,
                PIN_BA,
                PIN_SDR_AD,
                PIN_RAS_N,
                PIN_CAS_N,
                PIN_WE_N,
                PIN_DQM,
                PIN_DQI,

                // phy interface.
                PIN_PHY_RST_N,
                PIN_GTX_CLK,
                PIN_RX_CLK,
                PIN_TX_CLK,
                PIN_TX_ER,
                PIN_TX_EN,
                PIN_TXD,
                PIN_RX_ER,
                PIN_RX_DV,
                PIN_RXD,
                PIN_PHY_CRS,
                PIN_PHY_COL,
                PIN_PHY_SPEED
                );
//--------------------parameters--------------------//
//
//--------------------------------------------------//

//--------------------wires-------------------------//
// PCI Interface.
input         PIN_PCICLK;       // PCI Clock.
inout         PIN_FRAME_N;      // PCI Cycle Frame.
inout         PIN_IRDY_N;       // Initiator Ready.
input         PIN_IDSEL;        // PCI ID Select.
inout         PIN_DEVSEL_N;     // PCI Device Select.
inout         PIN_TRDY_N;       // Target Ready.
inout         PIN_STOP_N;       // PCI Bus Stop.
inout  [31:0] PIN_PCI_AD;       // PCI Address / Data Bus.
inout  [3:0]  PIN_CBE_N;        // PCI Command / Byte Enables.
output        PIN_REQ_N;        // PCI Bus Request.
input         PIN_GNT_N;        // PCI Bus Grant.
inout         PIN_PAR;          // PCI Bus Parity.
inout         PIN_PERR_N;       // PCI Request From Conntroller.
output        PIN_SERR_N;       // System Error.
output        PIN_INTA_N;

// SDRAM Interface.
output        PIN_SDRAMCLK;     // SDRAM Clock.
output        PIN_CS_N;         // SDRAM Chip Select.
output        PIN_CKE;          // SDRAM Clock Enable.
output [1:0]  PIN_BA;           // SDRAM Bank Select Address.
output [11:0] PIN_SDR_AD;       // SDRAM Address.
output        PIN_RAS_N;        // SDRAM Row Address Strobe.
output        PIN_CAS_N;        // SDRAM Column Address Strobe.
output        PIN_WE_N;         // SDRAM Write Enable.
output [1:0]  PIN_DQM;          // SDRAM Data InOut Mask.
inout  [15:0] PIN_DQI;          // SDRAM Data InOut.

// PHY TX/RX Interface.
output        PIN_PHY_RST_N;    // PHY Reset.
output        PIN_GTX_CLK;      // Giga TX Clock.
input         PIN_RX_CLK;       // Mega RX Clock.
input         PIN_TX_CLK;       // Mega TX Clock.
output        PIN_TX_ER;
output        PIN_TX_EN;
output [7:0]  PIN_TXD;          // PHY TX Data.
input         PIN_RX_ER;
input         PIN_RX_DV;
input  [7:0]  PIN_RXD;          // PHY RX Data.
input         PIN_PHY_CRS;
input         PIN_PHY_COL;
output [2:0]  PIN_PHY_SPEED;

// MISC.

// internal.
wire [31:0] l_ad_i;
wire [3:0]  l_cbe_ni;
wire        lm_req32_n;
wire        lm_last_n;
wire        lm_rdy_n;
wire        lt_rdy_n;
wire        lt_abort_n;
wire        lt_disc_n;
wire        lirq_n;
wire [31:0] l_adr_o;
wire [31:0] l_dat_o;
wire [3:0]  l_ben_o;
wire [3:0]  l_cmd_o;
wire        lm_adr_ack_n;
wire        lm_ack_n;
wire        lm_dxfr_n;
wire [9:0]  lm_tsr;
wire        lt_frame_n;
wire        lt_ack_n;
wire        lt_dxfr_n;
wire [11:0] lt_tsr;
wire [6:0]  cmd_reg;
wire [6:0]  stat_reg;
wire [7:0]  cache;

//--------------------------------------------------//

// pci core
// src/rtl/pci/altera_pci32_core.v
altera_pci32_core inst_altera_pci32_core(
                    .clk        (PIN_PCICLK     ),
	                .framen     (PIN_FRAME_N    ),
	                .irdyn      (PIN_IRDY_N     ),
	                .idsel      (PIN_IDSEL      ),
	                .devseln    (PIN_DEVSEL_N   ),
	                .trdyn      (PIN_TRDY_N     ),
	                .stopn      (PIN_STOP_N     ),
	                .ad         (PIN_PCI_AD     ),
	                .cben       (PIN_CBE_N      ),
	                .reqn       (PIN_REQ_N      ),
	                .gntn       (PIN_GNT_N      ),
	                .par        (PIN_PAR        ),
	                .perrn      (PIN_PERR_N     ),
	                .serrn      (PIN_SERR_N     ),
	                .intan      (PIN_INTA_N     ),
	                .rstn       (),

	                .l_adi      (l_ad_i         ),
	                .l_cbeni    (l_cbe_ni       ),
	                .lm_req32n  (lm_req32_n     ),
	                .lm_lastn   (lm_last_n      ),
	                .lm_rdyn    (lm_rdy_n       ),
	                .lt_rdyn    (lt_rdy_n       ),
	                .lt_abortn  (lt_abort_n     ),
	                .lt_discn   (lt_disc_n      ),
	                .lirqn      (lirq_n         ),
	                .l_adro     (l_adr_o        ),
	                .l_dato     (l_dat_o        ),
	                .l_beno     (l_ben_o        ),
	                .l_cmdo     (l_cmd_o        ),
	                .lm_adr_ackn(lm_adr_ack_n   ),
	                .lm_ackn    (lm_ack_n       ),
	                .lm_dxfrn   (lm_dxfr_n      ),
	                .lm_tsr     (lm_tsr         ),
	                .lt_framen  (lt_frame_n     ),
	                .lt_ackn    (lt_ack_n       ),
	                .lt_dxfrn   (lt_dxfr_n      ),
	                .lt_tsr     (lt_tsr         ),
	                .cmd_reg    (cmd_reg        ),
	                .stat_reg   (stat_reg       ),
	                .cache      (cache          )
                    );

endmodule
